Field of the Technology
The technology disclosed relates to patterned strips of material and contact areas on integrated circuits and their fabrication, including the use of multiple patterning methods to fabricate integrated circuits by which access to the strips of material formed thereby is facilitated.
Description of Related Art
Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits, so as to increase the density of the individual components and consequently enhance the functionality of an integrated circuit. The minimum pitch on an integrated circuit (the minimum distance between the same points of two adjacent structures of the same type, e.g., two adjacent gate conductors) is often used as a representative measure of the circuit's density.
Increases in circuit density often are limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is related to its resolution capacity.
The sum of the minimum feature width and minimum space width producible with a given piece of photolithographic equipment is the minimum pitch that the piece of equipment can produce. The minimum feature width can often times be approximately equal to the minimum space width, so the minimum pitch that can be produced with a given piece of photolithographic equipment is approximately equal to double the minimum feature width that it can produce.
One way to reduce the pitch of an integrated circuit device below that of the minimum pitch produced lithographically is through the use of double or quadruple patterning, sometimes referred to as multiple patterning herein. Through this method a single mask is typically used to create a series of parallel strips of material on the substrate. Different methods can then be used to transform each parallel strip of material into multiple parallel strips of material. The various methods typically use a series of deposition and etching steps to do so. Different methods are discussed in Xie, Peng and Smith, Bruce W., “Analysis of Higher-Order Pitch Division for Sub-32 nm Lithography”, Optical Microlithography XXII, Proc. of SPIE Vol. 7274, 72741Y, © 2009 SPIE.
Strips of material at a level are connected to another level through interlayer connectors that land on the landing areas. The interlayer connectors are formed using different patterning steps, that may have larger minimum pitch than the patterning steps used for the denser strips. As the parallel strips of material are scaled down by multiple patterning processes for higher density, a pitch required of the landing areas for interlayer connectors that connect the parallel strips becomes greater than a pitch of the parallel strips of material.
It is desirable to provide technology which can create landing areas that have a pitch greater than a pitch of the parallel strips of material without relaxing the pitch of the parallel strips of material, which can be the minimum pitch that can be produced with a given piece of photolithographic equipment.